Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

A 4-way multithreaded 8-way superscalar RISC microprocessor was proposed that implements the Alpha instruction set in a 0.125 mu m partially depleted silicon on insulator (SOI) technology. A 4-way simultaneous multithreading (SMT) increasing the utilization of the 8 integer and 4 floating point execution units by allowing concurrent execution of upto 4 independent program threads was implemented. SMT was implemented by adding circuitry to maintain the 4 independent program counters and select a single thread each cycle for fetch from the instruction cache. An age mask vector was used to avoid critical paths from the first in first out (FIFO) structure employed on the processor.