Exploration of Scandium Doping in SbTe for Phase Change Memory Application
In this work, we fabricate and electrically demonstrate a 65-nm technology-compatible Phase change memory (PCM) pillar device using Sc-doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on a 300-mm wafer in the 1T1R configuration. ST was chosen over GST to achieve a higher speed...
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| Veröffentlicht in: | IEEE transactions on electron devices 2022-11, Vol.69 (11), p.6106-6112 |
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| creator | Barci, Marinela Leonelli, Daniele Zhou, Xue Wang, Xiaojie Garbin, Daniele Jayakumar, Ganesh Witters, Thomas Vergel, Nathali Franchina Kundu, Shreya Palayam, Senthil Vadakupudhu Jiao, Huifang Wu, Hao Kar, Gouri Sankar |
| description | In this work, we fabricate and electrically demonstrate a 65-nm technology-compatible Phase change memory (PCM) pillar device using Sc-doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on a 300-mm wafer in the 1T1R configuration. ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to 1~\mu \text{s} for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. The fabricated devices show the potential to extend the PCM technology toward high-speed storage class memory (SCM) applications. |
| doi_str_mv | 10.1109/TED.2022.3209639 |
| format | Article |
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ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to <inline-formula> <tex-math notation="LaTeX">1~\mu \text{s} </tex-math></inline-formula> for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. The fabricated devices show the potential to extend the PCM technology toward high-speed storage class memory (SCM) applications.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2022.3209639</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Chalcogenide ; Chalcogenides ; Crystallization ; Doping ; doping Sc ; Electrodes ; emerging memory technology ; Endurance ; GeSeTe ; Knobs ; nonvolatile memory ; Performance evaluation ; Phase change materials ; Phase change memory (PCM) ; Resistance ; SbTe (ST) ; Scandium ; storage class memory (SCM) ; Switches ; Switching</subject><ispartof>IEEE transactions on electron devices, 2022-11, Vol.69 (11), p.6106-6112</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c206t-9cbcc58d4730da9004d001fddc754412f63cd5061bf2ac2e048e85d406f7cf0c3</citedby><cites>FETCH-LOGICAL-c206t-9cbcc58d4730da9004d001fddc754412f63cd5061bf2ac2e048e85d406f7cf0c3</cites><orcidid>0000-0001-5557-8879 ; 0000-0002-5884-1043 ; 0000-0002-0855-3377 ; 0000-0001-8235-8695 ; 0000-0002-8528-9469</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9912377$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9912377$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Barci, Marinela</creatorcontrib><creatorcontrib>Leonelli, Daniele</creatorcontrib><creatorcontrib>Zhou, Xue</creatorcontrib><creatorcontrib>Wang, Xiaojie</creatorcontrib><creatorcontrib>Garbin, Daniele</creatorcontrib><creatorcontrib>Jayakumar, Ganesh</creatorcontrib><creatorcontrib>Witters, Thomas</creatorcontrib><creatorcontrib>Vergel, Nathali Franchina</creatorcontrib><creatorcontrib>Kundu, Shreya</creatorcontrib><creatorcontrib>Palayam, Senthil Vadakupudhu</creatorcontrib><creatorcontrib>Jiao, Huifang</creatorcontrib><creatorcontrib>Wu, Hao</creatorcontrib><creatorcontrib>Kar, Gouri Sankar</creatorcontrib><title>Exploration of Scandium Doping in SbTe for Phase Change Memory Application</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>In this work, we fabricate and electrically demonstrate a 65-nm technology-compatible Phase change memory (PCM) pillar device using Sc-doped SbTe (ST) instead of GeSbTe (GST), for the first time fabricated on a 300-mm wafer in the 1T1R configuration. ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to <inline-formula> <tex-math notation="LaTeX">1~\mu \text{s} </tex-math></inline-formula> for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. The fabricated devices show the potential to extend the PCM technology toward high-speed storage class memory (SCM) applications.</description><subject>Chalcogenide</subject><subject>Chalcogenides</subject><subject>Crystallization</subject><subject>Doping</subject><subject>doping Sc</subject><subject>Electrodes</subject><subject>emerging memory technology</subject><subject>Endurance</subject><subject>GeSeTe</subject><subject>Knobs</subject><subject>nonvolatile memory</subject><subject>Performance evaluation</subject><subject>Phase change materials</subject><subject>Phase change memory (PCM)</subject><subject>Resistance</subject><subject>SbTe (ST)</subject><subject>Scandium</subject><subject>storage class memory (SCM)</subject><subject>Switches</subject><subject>Switching</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtLAzEURoMoWKt7wU3A9dSbxySTZan1RUWhdR3SPNqUdjJmWrD_3qktri4XvvPdy0HolsCAEFAPs_HjgAKlA0ZBCabOUI-UpSyU4OIc9QBIVShWsUt01barbhWc0x56G_8065TNNqYap4Cn1tQu7jb4MTWxXuBY4-l85nFIGX8uTevxaGnqhcfvfpPyHg-bZh3tH36NLoJZt_7mNPvo62k8G70Uk4_n19FwUlgKYlsoO7e2rByXDJxRANx13wTnrCw5JzQIZl0JgswDNZZ64JWvSsdBBGkDWNZH98feJqfvnW-3epV2ue5OaiqpBF5KSrsUHFM2p7bNPugmx43Je01AH4zpzpg-GNMnYx1yd0Si9_4_rhShTEr2C80RZh4</recordid><startdate>20221101</startdate><enddate>20221101</enddate><creator>Barci, Marinela</creator><creator>Leonelli, Daniele</creator><creator>Zhou, Xue</creator><creator>Wang, Xiaojie</creator><creator>Garbin, Daniele</creator><creator>Jayakumar, Ganesh</creator><creator>Witters, Thomas</creator><creator>Vergel, Nathali Franchina</creator><creator>Kundu, Shreya</creator><creator>Palayam, Senthil Vadakupudhu</creator><creator>Jiao, Huifang</creator><creator>Wu, Hao</creator><creator>Kar, Gouri Sankar</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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ST was chosen over GST to achieve a higher speed and endurance due to its faster crystallization speed and reduced volume variation during switching. Detailed knobs on how to improve stack in terms of CD, thickness (of electrode and chalcogenide material), and Sc doping are presented. The optimized stack shows ac switching from 300 ns to <inline-formula> <tex-math notation="LaTeX">1~\mu \text{s} </tex-math></inline-formula> for SET and RESET with current in the order of milliamperes and programming voltage less than 2.5 V. The endurance shows marginal memory window degradation up to 1E8 cycles and more than 1-h retention at 85° is achieved for the optimized stack of C:Si/50-nm ST:Sc 6%. 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| subjects | Chalcogenide Chalcogenides Crystallization Doping doping Sc Electrodes emerging memory technology Endurance GeSeTe Knobs nonvolatile memory Performance evaluation Phase change materials Phase change memory (PCM) Resistance SbTe (ST) Scandium storage class memory (SCM) Switches Switching |
| title | Exploration of Scandium Doping in SbTe for Phase Change Memory Application |
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