A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC

This paper presents a novel subranging Sigma-Delta ADC using a relaxation Current-Controlled Oscillator (ICO). The instantaneous frequency of the ICO at the sampling instant determines its time resolution and hence its quantization error, while its average frequency determines its power dissipation. Therefore, running the ICO at nominally lower frequency for most of the sampling period while increasing its frequency close to the sampling instant achieves high resolution and low power consumption. This idea is similar to the strategy employed by athletes in a race where they speed-up close to the finish line to gain a clear lead from others. A prototype ADC is designed and fabricated in TSMC 180nm CMOS technology. It achieves an ENOB of 11.9 bits consuming 10~\mu \text{W} of power from a 1.8V supply and occupies an active area of 0.06 mm 2, which corresponds to a Schreier FoM of 156.8 dB and a Walden FoM of 625 fJ/conversion cycle.