A Fast Method to Estimate Through-Bump Current for Power Delivery Verification

Due to the mismatch between the package scaling and the relentless silicon technology scaling, the limited power supply bumps have to bear more stresses on bump reliability. A too high through-bump current may induce increased thermal and mechanical issues, thereby damaging the integrity of solder joint micro-structure. Thus, it is critical to analyze the through-bump current under different test scenarios at sign off to ensure bump integrity. Since the full chip power delivery verification needs to solve a linear system with billions of nodes, it is then very time-and resource-consuming to repeatedly conduct such bump integrity check during ECO. In this paper, we present a fast through-bump current estimation methodology for power delivery verification, which can significantly reduce the computational complexity while maintaining accuracy. Experimental results demonstrate that the proposed methodology can achieve very high accuracy with a relative error of around 0.6% and a maximum error of around 1.5% across 4 different designs with 1-2 orders of magnitude speed-up.