Total dose radiation experiments in CMOS/SOI 4 Kb SRAM

Total dose radiation experiments in CMOS/SOI 4 Kb SRAM

This paper describes the total dose radiation performance of CMOS/SOI 4 Kb SRAMs fabricated in a radiation hardened partially depleted SOI CMOS technology. The SRAM adopts 1 K/spl times/4 architecture. It achieves a fast access time 30 ns and chip size 3.6 mm/spl times/3.84 mm. Memory functionality...

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Bibliographische Detailangaben
Hauptverfasser: Liu Yunlong, Liu Xinyu, Hai Chaohe, Sun Haifeng, Han Zhengsheng, Qian He
Format: Tagungsbericht
Sprache:eng ; jpn
Schlagworte:
Circuits
CMOS technology
Decoding
Fabrication
Isolation technology
Microelectronics
Power supplies
Radiation effects
Radiation hardening
Random access memory
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Zusammenfassung:This paper describes the total dose radiation performance of CMOS/SOI 4 Kb SRAMs fabricated in a radiation hardened partially depleted SOI CMOS technology. The SRAM adopts 1 K/spl times/4 architecture. It achieves a fast access time 30 ns and chip size 3.6 mm/spl times/3.84 mm. Memory functionality does well after a total dose irradiation up to 5/spl times/10/sup 5/ rad(Si) under 3 V power supply. This meets the needs in military and aerospace fields. It is the first time that the radiation effects on SOI VLSI were investigated in China.
DOI:10.1109/ICSICT.2001.981569