A 6-GHz Bandwidth Input Buffer Based on AC-Coupled Flipped Source Follower for 12-bit 8-GS/s ADC in 28-nm CMOS

This brief presents an input buffer based on AC-coupled flipped source follower (SF) for a 12-bit 8-GS/s time-interleaved (TI) ADC. The flipped SF can drive the ADC's sampling capacitance with high linearity because the input MOS's drain current is almost independent of the load capacitance. In addition, the inherent feedback reduces the input buffer's output impedance, which improves the bandwidth when driving the complex wiring network of TI ADCs. The proposed AC-coupling structure enlarges the input signal range of the flipped SF extensively, making it practical to be used for high-speed ADCs. A compensation capacitor is used to compensate for the nonlinear parasitic capacitance of the input MOS to further improve the linearity. An 8-channel 12-bit 8GS/s TI ADC prototype with the proposed input buffer is implemented in a 28-nm mixed-signal CMOS process. Measured results show that the input bandwidth of the input buffer exceeds 6 GHz with 137-mW power supply. The ADC achieves SFDR of 68 dBFS and SNDR of 54.9 dB with 3.9-GHz, −1-dBFS input signal under 8-GS/s sampling rate. The total power consumption of the ADC is 1.05 W.