A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

A high performance 0.13 /spl mu/m SOI CMOS technology with a 70 nm silicon film and with a second generation low-k Cu BEOL

This paper describes a second generation 1.2 V high performance 0.13 /spl mu/m SOI technology. Aggressive ground rules and a tungsten damascene local interconnect render the densest 6T 0.13 /spl mu/m SRAM reported to date with a cell area of 1.80 /spl mu/m/sup 2/. 248 nm lithography is used for all...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Sleight, J.W., Varekamp, P.R., Lustig, N., Adkisson, J., Allen, A., Bula, O., Chen, X., Chou, T., Chu, W., Fitzsimmons, J., Gabor, A., Gates, S., Jamison, P., Khare, M., Lai, L., Lee, J., Narasimha, S., Ellis-Monaghan, J., Peterson, K., Rauch, S., Shukla, S., Smeys, P., Su, T.-C., Quinlan, J., Vayshenker, A., Ward, B., Womack, S., Barth, E., Biery, G., Davis, C., Ferguson, R., Goldblatt, R., Leobandung, E., Weiser, J., Yang, I., Agnello, P.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitance
CMOS technology
Delay
Dielectrics
Hot carriers
MOS devices
Nitrogen
Semiconductor films
Silicon
Threshold voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper describes a second generation 1.2 V high performance 0.13 /spl mu/m SOI technology. Aggressive ground rules and a tungsten damascene local interconnect render the densest 6T 0.13 /spl mu/m SRAM reported to date with a cell area of 1.80 /spl mu/m/sup 2/. 248 nm lithography is used for all critical levels. Interconnect performance requirements are achieved by using up to 8 levels of Cu wiring and an advanced BEOL process with low-k interlevel dielectrics and SiC barrier layers.
DOI:10.1109/IEDM.2001.979476