Analytical Loss Model for Three-Phase 1200V SiC MOSFET Inverter Drive System Utilizing Miller Capacitor-Based dv/dt-Limitation

Next-generationVariable Speed Drive (VSD) systems utilize SiC MOSFETs to achieve both high efficiency through reduced bridge-leg losses and high power density through an order-of-magnitude increase in switching frequency or reduction of the DC-link capacitance. These systems, however, must contend with the high voltage slew rate (\text{d} {v}_\text{DS}/\text{d}t) of these next-generation power semiconductors, especially in the context of protecting the motor from partial discharge phenomena, surge voltages from cable reflections, and unequal distribution of the voltage across motor windings. We assess the attractiveness of an external Miller capacitor across the bridge-leg power semiconductors to limit the maximum voltage slew rate in a system. To evaluate this technique, we propose a maximum \text{d}v_\text{DS}/\text{d}t model, finding that the maximum turn-on slew rate occurs at Zero-Current Switching (ZCS) with an increase in \text{d}v_\text{DS}/\text{d}t as the device junction temperature increases. During the turn-off transition, the applied \text{d}v_\text{DS}/\text{d}t saturates at a particular current. We then find a switching loss model, arriving at a piecewise-linear dependence of bridge-leg switching losses on current under \text{d}v_\text{DS}/\text{d}t-limited conditions, a finding that runs counter to the widely-utilized quadratic current dependence. The proposed models are validated on a SiC MOSFET bridge-leg designed for a 10 \,\mathrm{k}\mathrm{W} 800 \,\mathrm{V} DC-link Variable Speed Drive (VSD) system with a switching frequency of 16 \,{\mathrm kHz}, where the Miller capacitor-based technique achieves lower losses (for the same maximum \text{d}v_\text{DS}/\text{d}t) than a gate resistor-only \text{d}v_\text{DS}/\text{d}t limiting approach.