Tackling test trade-offs from design, manufacturing to market using economic modeling
This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and...
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| creator | Volkerink, E.H. Khoche, A. Kamas, L.A. Rivoir, J. Kerkhoff, H.G. |
| description | This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches. |
| doi_str_mv | 10.1109/TEST.2001.966736 |
| format | Conference Proceeding |
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The modeling methodology will be illustrated on various test approaches.</description><subject>Cost function</subject><subject>Economic forecasting</subject><subject>Laboratories</subject><subject>Logic testing</subject><subject>Production</subject><subject>Pulp manufacturing</subject><subject>Semiconductor device manufacture</subject><subject>Semiconductor device testing</subject><subject>Time to market</subject><subject>Virtual manufacturing</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>0780371690</isbn><isbn>9780780371699</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkEtLA0EQhAcfYBK9i6f5AW7s7sm8jhLiAwIe3JzDZLYnrMnuys7m4L83MZ6KKoqPooS4R5gign8qF5_llABw6o2xylyIESnrCiINl2IM1oGyaDxciRGC84XSyt-Icc5fAASaYCRWZYi7fd1u5cB5kEMfKi66lLJMfdfIinO9bR9lE9pDCnE49H_V7hj0Ox7kIZ88x67tmjrKpqv4BLsV1ynsM9_960SsXhbl_K1Yfry-z5-XRY2WhiKFKqSNScCEFVrH6DZWz3QMG8ukgvKkZ4pc9B6MJjxu01E5hEgGMQQ1EQ9nbs3M6---Ps76WZ_fUL-NhVJj</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Volkerink, E.H.</creator><creator>Khoche, A.</creator><creator>Kamas, L.A.</creator><creator>Rivoir, J.</creator><creator>Kerkhoff, H.G.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>Tackling test trade-offs from design, manufacturing to market using economic modeling</title><author>Volkerink, E.H. ; Khoche, A. ; Kamas, L.A. ; Rivoir, J. ; Kerkhoff, H.G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-fadafb6f0e21d178e18b7545cab7e23a39254328c9906521ade5c3810c2611aa3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Cost function</topic><topic>Economic forecasting</topic><topic>Laboratories</topic><topic>Logic testing</topic><topic>Production</topic><topic>Pulp manufacturing</topic><topic>Semiconductor device manufacture</topic><topic>Semiconductor device testing</topic><topic>Time to market</topic><topic>Virtual manufacturing</topic><toplevel>online_resources</toplevel><creatorcontrib>Volkerink, E.H.</creatorcontrib><creatorcontrib>Khoche, A.</creatorcontrib><creatorcontrib>Kamas, L.A.</creatorcontrib><creatorcontrib>Rivoir, J.</creatorcontrib><creatorcontrib>Kerkhoff, H.G.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Volkerink, E.H.</au><au>Khoche, A.</au><au>Kamas, L.A.</au><au>Rivoir, J.</au><au>Kerkhoff, H.G.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Tackling test trade-offs from design, manufacturing to market using economic modeling</atitle><btitle>Proceedings International Test Conference 2001 (Cat. No.01CH37260)</btitle><stitle>TEST</stitle><date>2001</date><risdate>2001</risdate><spage>1098</spage><epage>1107</epage><pages>1098-1107</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>0780371690</isbn><isbn>9780780371699</isbn><abstract>This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches.</abstract><pub>IEEE</pub><doi>10.1109/TEST.2001.966736</doi><tpages>10</tpages></addata></record> |
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| identifier | ISSN: 1089-3539 |
| ispartof | Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.1098-1107 |
| issn | 1089-3539 2378-2250 |
| language | eng |
| recordid | cdi_ieee_primary_966736 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Cost function Economic forecasting Laboratories Logic testing Production Pulp manufacturing Semiconductor device manufacture Semiconductor device testing Time to market Virtual manufacturing |
| title | Tackling test trade-offs from design, manufacturing to market using economic modeling |
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