Tackling test trade-offs from design, manufacturing to market using economic modeling

This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches.