Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment

Bit fail maps of semiconductor memories are generated in a manufacturing environment during wafer test to identify process problems and for repair. Since bit fail map capabilities are expensive for high-speed testers and massive parallel test systems, component test is generating only pass/fail info...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Vollrath, J., Rooney, R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Costs Failure analysis Manufacturing processes Production Random access memory Semiconductor device manufacture Semiconductor device testing Semiconductor memory System testing Temperature
Online-Zugang:	Volltext bestellen
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