Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment

Bit fail maps of semiconductor memories are generated in a manufacturing environment during wafer test to identify process problems and for repair. Since bit fail map capabilities are expensive for high-speed testers and massive parallel test systems, component test is generating only pass/fail information. It is difficult to relate the pass/fail information to a process problem. This paper presents a test strategy and a software tool to construct pseudo bit fail maps from pass/fail information using a special test sequence. The pseudo bit fail map can be generated in a manufacturing environment and can be used for identifying process problems and doing physical failure analysis at the fail location.