GRAAL: a tool for highly dependable SRAMs generation

Presents a tool to achieve proper reliability levels in systems based on memories, allowing the automatic insertion of BIST architectures for both OFF-line and ON-line memory testing. While OFF-line memory testing was partially targeted by the available commercial tools, ON-line memory testing has s...

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Hauptverfasser: Chiusano, S., Di Natale, G., Prinetto, P., Bigongiari, F.
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creator Chiusano, S.
Di Natale, G.
Prinetto, P.
Bigongiari, F.
description Presents a tool to achieve proper reliability levels in systems based on memories, allowing the automatic insertion of BIST architectures for both OFF-line and ON-line memory testing. While OFF-line memory testing was partially targeted by the available commercial tools, ON-line memory testing has so far not been covered. The set of algorithms and architectures supported by the tool is not limited, and it can be easily extended to include innovative architectures and achieve the reliability requirements in any application. Using the tool, the designer can generate dependable memories, trading-off in the design process dependability properties and costs.
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fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_966640</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>966640</ieee_id><sourcerecordid>966640</sourcerecordid><originalsourceid>FETCH-LOGICAL-i172t-80cd2587a91385b7f97ace9915933417d10360cc7f8a5c1f7ab92172465e26153</originalsourceid><addsrcrecordid>eNotj8tKw0AUQAcfYFrdi6v5gcR7ZzKP6y6UWoWI0MZ1mSQ3bSQmJcmmf69QV2d1DhwhHhESRKDnYr0rEgWACVlrU7gSkdLOx0oZuBYLcB60Q0twIyIET7E2mu7EYpq-ARQYBZFIN9ssy19kkPMwdLIZRnlsD8fuLGs-cV-HsmO522Yfkzxwz2OY26G_F7dN6CZ--OdSfL2ui9VbnH9u3ldZHrfo1Bx7qGplvAuE2pvSNeRCxURoSOsUXY2gLVSVa3wwFTYulKT-zNQaVhaNXoqnS7dl5v1pbH_CeN5fZvUvlUlDcQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>GRAAL: a tool for highly dependable SRAMs generation</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chiusano, S. ; Di Natale, G. ; Prinetto, P. ; Bigongiari, F.</creator><creatorcontrib>Chiusano, S. ; Di Natale, G. ; Prinetto, P. ; Bigongiari, F.</creatorcontrib><description>Presents a tool to achieve proper reliability levels in systems based on memories, allowing the automatic insertion of BIST architectures for both OFF-line and ON-line memory testing. While OFF-line memory testing was partially targeted by the available commercial tools, ON-line memory testing has so far not been covered. The set of algorithms and architectures supported by the tool is not limited, and it can be easily extended to include innovative architectures and achieve the reliability requirements in any application. Using the tool, the designer can generate dependable memories, trading-off in the design process dependability properties and costs.</description><identifier>ISSN: 1089-3539</identifier><identifier>ISBN: 0780371690</identifier><identifier>ISBN: 9780780371699</identifier><identifier>EISSN: 2378-2250</identifier><identifier>DOI: 10.1109/TEST.2001.966640</identifier><language>eng</language><publisher>IEEE</publisher><subject>Automatic testing ; Built-in self-test ; Costs ; Fault detection ; Logic testing ; Memory architecture ; Process design ; Random access memory ; Space technology ; System testing</subject><ispartof>Proceedings International Test Conference 2001 (Cat. No.01CH37260), 2001, p.250-257</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/966640$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,4038,4039,27908,54903</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/966640$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chiusano, S.</creatorcontrib><creatorcontrib>Di Natale, G.</creatorcontrib><creatorcontrib>Prinetto, P.</creatorcontrib><creatorcontrib>Bigongiari, F.</creatorcontrib><title>GRAAL: a tool for highly dependable SRAMs generation</title><title>Proceedings International Test Conference 2001 (Cat. No.01CH37260)</title><addtitle>TEST</addtitle><description>Presents a tool to achieve proper reliability levels in systems based on memories, allowing the automatic insertion of BIST architectures for both OFF-line and ON-line memory testing. While OFF-line memory testing was partially targeted by the available commercial tools, ON-line memory testing has so far not been covered. The set of algorithms and architectures supported by the tool is not limited, and it can be easily extended to include innovative architectures and achieve the reliability requirements in any application. Using the tool, the designer can generate dependable memories, trading-off in the design process dependability properties and costs.</description><subject>Automatic testing</subject><subject>Built-in self-test</subject><subject>Costs</subject><subject>Fault detection</subject><subject>Logic testing</subject><subject>Memory architecture</subject><subject>Process design</subject><subject>Random access memory</subject><subject>Space technology</subject><subject>System testing</subject><issn>1089-3539</issn><issn>2378-2250</issn><isbn>0780371690</isbn><isbn>9780780371699</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj8tKw0AUQAcfYFrdi6v5gcR7ZzKP6y6UWoWI0MZ1mSQ3bSQmJcmmf69QV2d1DhwhHhESRKDnYr0rEgWACVlrU7gSkdLOx0oZuBYLcB60Q0twIyIET7E2mu7EYpq-ARQYBZFIN9ssy19kkPMwdLIZRnlsD8fuLGs-cV-HsmO522Yfkzxwz2OY26G_F7dN6CZ--OdSfL2ui9VbnH9u3ldZHrfo1Bx7qGplvAuE2pvSNeRCxURoSOsUXY2gLVSVa3wwFTYulKT-zNQaVhaNXoqnS7dl5v1pbH_CeN5fZvUvlUlDcQ</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Chiusano, S.</creator><creator>Di Natale, G.</creator><creator>Prinetto, P.</creator><creator>Bigongiari, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>2001</creationdate><title>GRAAL: a tool for highly dependable SRAMs generation</title><author>Chiusano, S. ; Di Natale, G. ; Prinetto, P. ; Bigongiari, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i172t-80cd2587a91385b7f97ace9915933417d10360cc7f8a5c1f7ab92172465e26153</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Automatic testing</topic><topic>Built-in self-test</topic><topic>Costs</topic><topic>Fault detection</topic><topic>Logic testing</topic><topic>Memory architecture</topic><topic>Process design</topic><topic>Random access memory</topic><topic>Space technology</topic><topic>System testing</topic><toplevel>online_resources</toplevel><creatorcontrib>Chiusano, S.</creatorcontrib><creatorcontrib>Di Natale, G.</creatorcontrib><creatorcontrib>Prinetto, P.</creatorcontrib><creatorcontrib>Bigongiari, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chiusano, S.</au><au>Di Natale, G.</au><au>Prinetto, P.</au><au>Bigongiari, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>GRAAL: a tool for highly dependable SRAMs generation</atitle><btitle>Proceedings International Test Conference 2001 (Cat. No.01CH37260)</btitle><stitle>TEST</stitle><date>2001</date><risdate>2001</risdate><spage>250</spage><epage>257</epage><pages>250-257</pages><issn>1089-3539</issn><eissn>2378-2250</eissn><isbn>0780371690</isbn><isbn>9780780371699</isbn><abstract>Presents a tool to achieve proper reliability levels in systems based on memories, allowing the automatic insertion of BIST architectures for both OFF-line and ON-line memory testing. While OFF-line memory testing was partially targeted by the available commercial tools, ON-line memory testing has so far not been covered. The set of algorithms and architectures supported by the tool is not limited, and it can be easily extended to include innovative architectures and achieve the reliability requirements in any application. Using the tool, the designer can generate dependable memories, trading-off in the design process dependability properties and costs.</abstract><pub>IEEE</pub><doi>10.1109/TEST.2001.966640</doi><tpages>8</tpages></addata></record>
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subjects Automatic testing
Built-in self-test
Costs
Fault detection
Logic testing
Memory architecture
Process design
Random access memory
Space technology
System testing
title GRAAL: a tool for highly dependable SRAMs generation
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T12%3A34%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=GRAAL:%20a%20tool%20for%20highly%20dependable%20SRAMs%20generation&rft.btitle=Proceedings%20International%20Test%20Conference%202001%20(Cat.%20No.01CH37260)&rft.au=Chiusano,%20S.&rft.date=2001&rft.spage=250&rft.epage=257&rft.pages=250-257&rft.issn=1089-3539&rft.eissn=2378-2250&rft.isbn=0780371690&rft.isbn_list=9780780371699&rft_id=info:doi/10.1109/TEST.2001.966640&rft_dat=%3Cieee_6IE%3E966640%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=966640&rfr_iscdi=true