A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse

A multigigabit DRAM technology was developed that features a low-noise 6F/sup 2/ open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be use...

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Veröffentlicht in:	IEEE journal of solid-state circuits 2001-11, Vol.36 (11), p.1721-1727
Hauptverfasser:	Takahashi, T., Sekiguchi, T., Takemura, R., Narui, S., Fujisawa, H., Miyatake, S., Morino, M., Arai, K., Yamada, S., Shukuri, S., Nakamura, M., Tadaki, Y., Kajigaya, K., Kimura, K., Itoh, K.
Format:	Artikel
Sprache:	eng
Schlagworte:	Assembly Associate members Fuses Lead compounds Low voltage Packaging Random access memory Semiconductor device noise Testing Timing
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Beschreibung
Zusammenfassung:	A multigigabit DRAM technology was developed that features a low-noise 6F/sup 2/ open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-/spl mu/m 180-mm/sup 2/ 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm/sup 2/, 200-MHz array-cycle, 256-Mb test chip with 0.109-/spl mu/m/sup 2/ cells.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/4.962294