A Compact Model for Nanowire Tunneling-FETs

The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simu...

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Veröffentlicht in:	IEEE transactions on electron devices 2022-01, Vol.69 (1), p.419-426
Hauptverfasser:	Lu, Bin, Wang, Dawei, Cui, Yan, Li, Zhu, Chai, Guoqiang, Dong, Linpeng, Zhou, Jiuren, Wang, Guilei, Miao, Yuanhao, Lv, Zhijun, Lu, Hongliang
Format:	Artikel
Sprache:	eng
Schlagworte:	BTBT Capacitance Electric potential Field effect transistors gate-all-around (GAA) Gates (circuits) Integrated circuit modeling Iterative methods Logic gates nanowire Nanowires Semiconductor device modeling Semiconductor devices Silicon Simulation SPICE TFETs tunnel field-effect transistor (TFET) Tunneling
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