Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS ICs. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS ICs....
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| container_end_page | 116 vol.1 |
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| container_start_page | 113 |
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| creator | Ming-Dou Ker Hsin-Chin Jiang Jeng-Jie Peng Tzay-Luen Shieh |
| description | A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS ICs. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS ICs. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "guard ring automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately. |
| doi_str_mv | 10.1109/ICECS.2001.957690 |
| format | Conference Proceeding |
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| identifier | ISBN: 9780780370579 |
| ispartof | ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), 2001, Vol.1, p.113-116 vol.1 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | CMOS analog integrated circuits CMOS integrated circuits CMOS process CMOS technology Equivalent circuits Integrated circuit layout Laboratories MOS devices Pins Variable structure systems |
| title | Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's |
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