Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's

A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS ICs. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS ICs....

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS analog integrated circuits CMOS integrated circuits CMOS process CMOS technology Equivalent circuits Integrated circuit layout Laboratories MOS devices Pins Variable structure systems
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS ICs. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS ICs. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "guard ring automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.
DOI:	10.1109/ICECS.2001.957690