TDNVRAM/sup TM/: methodology and architecture of a nonvolatile-memory technology development testchip

In today's flash technology development, most of the critical issues arise at the 'array level', not at the 'device level'. Problems such as read disturb, program/erase endurance and erratic bits are critical for the release of a given technology into production and its yield. However, these problems are generally tackled relatively late in the development cycle. This paper proposes a novel methodology and testchip architecture aimed to address the issues mentioned above very early in the technology development cycle.