A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience
This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achiev...
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Veröffentlicht in: | IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2022-01, Vol.69 (1), p.366-377 |
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creator | Zhang, Jieyun Xu, Chongyao Law, Man-Kay Jiang, Yang Zhao, Xiaojin Mak, Pui-In Martins, Rui P. |
description | This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of 6845\mu \text{m}^{2} . Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across 1.06\sim 1.55V and - 30\sim 125^{\circ }\text{C} , while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using 80\times 80\times 80 artificial neural network (ANN) with 1M CPRs as training set. |
doi_str_mv | 10.1109/TCSI.2021.3114084 |
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The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of <inline-formula> <tex-math notation="LaTeX">6845\mu \text{m}^{2} </tex-math></inline-formula>. Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across <inline-formula> <tex-math notation="LaTeX">1.06\sim 1.55V </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">- 30\sim 125^{\circ }\text{C} </tex-math></inline-formula>, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using <inline-formula> <tex-math notation="LaTeX">80\times 80\times 80 </tex-math></inline-formula> artificial neural network (ANN) with 1M CPRs as training set.]]></description><identifier>ISSN: 1549-8328</identifier><identifier>EISSN: 1558-0806</identifier><identifier>DOI: 10.1109/TCSI.2021.3114084</identifier><identifier>CODEN: ITCSCH</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Amplification ; Amplifier chain ; Amplifiers ; Artificial neural networks ; Bias ; Bit error rate ; Chains ; Entropy ; Error analysis ; Gates (circuits) ; hardware security ; Learning theory ; Logic gates ; Machine learning ; machine learning attack ; Metal oxide semiconductors ; Modelling ; Multiplication ; Optimization ; Physical unclonable function ; physical unclonable function (PUF) ; Reliability ; Resistance ; Training ; Transistors ; Uniqueness ; Voltage</subject><ispartof>IEEE transactions on circuits and systems. I, Regular papers, 2022-01, Vol.69 (1), p.366-377</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2022</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c293t-d785bc6e201787f0cba0bcf4814ea4a2be23a8d2a51658017b6cc0225149c6ce3</citedby><cites>FETCH-LOGICAL-c293t-d785bc6e201787f0cba0bcf4814ea4a2be23a8d2a51658017b6cc0225149c6ce3</cites><orcidid>0000-0003-2577-4259 ; 0000-0002-9965-3516 ; 0000-0003-2821-648X ; 0000-0002-2799-1129 ; 0000-0001-7210-2661 ; 0000-0002-3579-8740</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9556517$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9556517$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zhang, Jieyun</creatorcontrib><creatorcontrib>Xu, Chongyao</creatorcontrib><creatorcontrib>Law, Man-Kay</creatorcontrib><creatorcontrib>Jiang, Yang</creatorcontrib><creatorcontrib>Zhao, Xiaojin</creatorcontrib><creatorcontrib>Mak, Pui-In</creatorcontrib><creatorcontrib>Martins, Rui P.</creatorcontrib><title>A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience</title><title>IEEE transactions on circuits and systems. I, Regular papers</title><addtitle>TCSI</addtitle><description><![CDATA[This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of <inline-formula> <tex-math notation="LaTeX">6845\mu \text{m}^{2} </tex-math></inline-formula>. Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across <inline-formula> <tex-math notation="LaTeX">1.06\sim 1.55V </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">- 30\sim 125^{\circ }\text{C} </tex-math></inline-formula>, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using <inline-formula> <tex-math notation="LaTeX">80\times 80\times 80 </tex-math></inline-formula> artificial neural network (ANN) with 1M CPRs as training set.]]></description><subject>Amplification</subject><subject>Amplifier chain</subject><subject>Amplifiers</subject><subject>Artificial neural networks</subject><subject>Bias</subject><subject>Bit error rate</subject><subject>Chains</subject><subject>Entropy</subject><subject>Error analysis</subject><subject>Gates (circuits)</subject><subject>hardware security</subject><subject>Learning theory</subject><subject>Logic gates</subject><subject>Machine learning</subject><subject>machine learning attack</subject><subject>Metal oxide semiconductors</subject><subject>Modelling</subject><subject>Multiplication</subject><subject>Optimization</subject><subject>Physical unclonable function</subject><subject>physical unclonable function (PUF)</subject><subject>Reliability</subject><subject>Resistance</subject><subject>Training</subject><subject>Transistors</subject><subject>Uniqueness</subject><subject>Voltage</subject><issn>1549-8328</issn><issn>1558-0806</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2022</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kE1Lw0AQhhdRsFZ_gHhZ8Jx2P5PNMQarhUqlH-pt2WwndmtM6m568N-b0OJpXobnnYEHoVtKRpSSdLzKl9MRI4yOOKWCKHGGBlRKFRFF4vM-izRSnKlLdBXCjhCWEk4H6C3DYjXOoapw9r2vXOnAR_nWuDp6MAE2-GO-wK_rCX537RYvW9_Un_jF2K2rAc_A-Np1i6xtjf3CCwiuclBbuEYXpakC3JzmEK0nj6v8OZrNn6Z5NossS3kbbRIlCxsDIzRRSUlsYUhhS6GoACMMK4BxozbMSBpL1UFFbC1hTFKR2tgCH6L74929b34OEFq9aw6-7l5qFjNKYslF2lH0SFnfhOCh1Hvvvo3_1ZToXp_u9elenz7p6zp3x44DgH8-lTKWNOF_c19pSA</recordid><startdate>202201</startdate><enddate>202201</enddate><creator>Zhang, Jieyun</creator><creator>Xu, Chongyao</creator><creator>Law, Man-Kay</creator><creator>Jiang, Yang</creator><creator>Zhao, Xiaojin</creator><creator>Mak, Pui-In</creator><creator>Martins, Rui P.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0003-2577-4259</orcidid><orcidid>https://orcid.org/0000-0002-9965-3516</orcidid><orcidid>https://orcid.org/0000-0003-2821-648X</orcidid><orcidid>https://orcid.org/0000-0002-2799-1129</orcidid><orcidid>https://orcid.org/0000-0001-7210-2661</orcidid><orcidid>https://orcid.org/0000-0002-3579-8740</orcidid></search><sort><creationdate>202201</creationdate><title>A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience</title><author>Zhang, Jieyun ; Xu, Chongyao ; Law, Man-Kay ; Jiang, Yang ; Zhao, Xiaojin ; Mak, Pui-In ; Martins, Rui P.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c293t-d785bc6e201787f0cba0bcf4814ea4a2be23a8d2a51658017b6cc0225149c6ce3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2022</creationdate><topic>Amplification</topic><topic>Amplifier chain</topic><topic>Amplifiers</topic><topic>Artificial neural networks</topic><topic>Bias</topic><topic>Bit error rate</topic><topic>Chains</topic><topic>Entropy</topic><topic>Error analysis</topic><topic>Gates (circuits)</topic><topic>hardware security</topic><topic>Learning theory</topic><topic>Logic gates</topic><topic>Machine learning</topic><topic>machine learning attack</topic><topic>Metal oxide semiconductors</topic><topic>Modelling</topic><topic>Multiplication</topic><topic>Optimization</topic><topic>Physical unclonable function</topic><topic>physical unclonable function (PUF)</topic><topic>Reliability</topic><topic>Resistance</topic><topic>Training</topic><topic>Transistors</topic><topic>Uniqueness</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Zhang, Jieyun</creatorcontrib><creatorcontrib>Xu, Chongyao</creatorcontrib><creatorcontrib>Law, Man-Kay</creatorcontrib><creatorcontrib>Jiang, Yang</creatorcontrib><creatorcontrib>Zhao, Xiaojin</creatorcontrib><creatorcontrib>Mak, Pui-In</creatorcontrib><creatorcontrib>Martins, Rui P.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhang, Jieyun</au><au>Xu, Chongyao</au><au>Law, Man-Kay</au><au>Jiang, Yang</au><au>Zhao, Xiaojin</au><au>Mak, Pui-In</au><au>Martins, Rui P.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience</atitle><jtitle>IEEE transactions on circuits and systems. I, Regular papers</jtitle><stitle>TCSI</stitle><date>2022-01</date><risdate>2022</risdate><volume>69</volume><issue>1</issue><spage>366</spage><epage>377</epage><pages>366-377</pages><issn>1549-8328</issn><eissn>1558-0806</eissn><coden>ITCSCH</coden><abstract><![CDATA[This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of <inline-formula> <tex-math notation="LaTeX">6845\mu \text{m}^{2} </tex-math></inline-formula>. Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across <inline-formula> <tex-math notation="LaTeX">1.06\sim 1.55V </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">- 30\sim 125^{\circ }\text{C} </tex-math></inline-formula>, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using <inline-formula> <tex-math notation="LaTeX">80\times 80\times 80 </tex-math></inline-formula> artificial neural network (ANN) with 1M CPRs as training set.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TCSI.2021.3114084</doi><tpages>12</tpages><orcidid>https://orcid.org/0000-0003-2577-4259</orcidid><orcidid>https://orcid.org/0000-0002-9965-3516</orcidid><orcidid>https://orcid.org/0000-0003-2821-648X</orcidid><orcidid>https://orcid.org/0000-0002-2799-1129</orcidid><orcidid>https://orcid.org/0000-0001-7210-2661</orcidid><orcidid>https://orcid.org/0000-0002-3579-8740</orcidid></addata></record> |
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subjects | Amplification Amplifier chain Amplifiers Artificial neural networks Bias Bit error rate Chains Entropy Error analysis Gates (circuits) hardware security Learning theory Logic gates Machine learning machine learning attack Metal oxide semiconductors Modelling Multiplication Optimization Physical unclonable function physical unclonable function (PUF) Reliability Resistance Training Transistors Uniqueness Voltage |
title | A 4T/Cell Amplifier-Chain-Based XOR PUF With Strong Machine Learning Attack Resilience |
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