Modeling superscalar processors via statistical simulation

Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple proce...

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Veröffentlicht in:Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques 2001, p.15-24
Hauptverfasser: Nussbaum, S., Smith, J.E.
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description Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple processor model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of modeling complexity. Both errors and convergence properties are studied in detail. A simple instruction model yields an average error of 8% compared with detailed simulation. A more detailed instruction model reduces the error to 5% but requires about three times as long to converge.
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fullrecord <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_ieee_primary_953284</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>953284</ieee_id><sourcerecordid>26791316</sourcerecordid><originalsourceid>FETCH-LOGICAL-i245t-97bd68efcf26091db4d4d0f2bbc3d734f9ff87bedd50679198ef5ea3b1dbbff13</originalsourceid><addsrcrecordid>eNotkM1LxDAQxQMquK57F089eWvNV9PG27K4KqzoYQVvJWkmEumXnVbwvzdS3-UxvN8MwyPkitGMMapvX7e7Y8YpZZnOBS_lCbmghdI5E0qUp2TFaKnTQqv3c7JB_KRRQitK5YrcPfcOmtB9JDgPMGJtGjMmw9jXgNiPmHwHk-BkpoBTiGGCoZ2bOPbdJTnzpkHY_PuavO3vj7vH9PDy8LTbHtLAZT6lurBOleBrzxXVzFnppKOeW1sLVwjptfdlYcG5nKpCMx3ZHIywEbXeM7EmN8vd-NXXDDhVbcAamsZ00M9Y8b8twVQErxcwAEA1jKE140-1VCJ-AZEEVwQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26791316</pqid></control><display><type>article</type><title>Modeling superscalar processors via statistical simulation</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Nussbaum, S. ; Smith, J.E.</creator><creatorcontrib>Nussbaum, S. ; Smith, J.E.</creatorcontrib><description>Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple processor model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of modeling complexity. Both errors and convergence properties are studied in detail. A simple instruction model yields an average error of 8% compared with detailed simulation. A more detailed instruction model reduces the error to 5% but requires about three times as long to converge.</description><identifier>ISSN: 1089-796X</identifier><identifier>ISSN: 1089-795X</identifier><identifier>ISBN: 0769513638</identifier><identifier>ISBN: 9780769513638</identifier><identifier>DOI: 10.1109/PACT.2001.953284</identifier><language>eng</language><publisher>IEEE</publisher><subject>Analytical models ; Computational modeling ; Computer errors ; Computer performance ; Computer simulation ; Convergence ; Discrete event simulation ; Predictive models ; Space exploration ; Statistics</subject><ispartof>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, 2001, p.15-24</ispartof><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/953284$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,4036,4037,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/953284$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Nussbaum, S.</creatorcontrib><creatorcontrib>Smith, J.E.</creatorcontrib><title>Modeling superscalar processors via statistical simulation</title><title>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques</title><addtitle>PACT</addtitle><description>Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple processor model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of modeling complexity. Both errors and convergence properties are studied in detail. A simple instruction model yields an average error of 8% compared with detailed simulation. A more detailed instruction model reduces the error to 5% but requires about three times as long to converge.</description><subject>Analytical models</subject><subject>Computational modeling</subject><subject>Computer errors</subject><subject>Computer performance</subject><subject>Computer simulation</subject><subject>Convergence</subject><subject>Discrete event simulation</subject><subject>Predictive models</subject><subject>Space exploration</subject><subject>Statistics</subject><issn>1089-796X</issn><issn>1089-795X</issn><isbn>0769513638</isbn><isbn>9780769513638</isbn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2001</creationdate><recordtype>article</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkM1LxDAQxQMquK57F089eWvNV9PG27K4KqzoYQVvJWkmEumXnVbwvzdS3-UxvN8MwyPkitGMMapvX7e7Y8YpZZnOBS_lCbmghdI5E0qUp2TFaKnTQqv3c7JB_KRRQitK5YrcPfcOmtB9JDgPMGJtGjMmw9jXgNiPmHwHk-BkpoBTiGGCoZ2bOPbdJTnzpkHY_PuavO3vj7vH9PDy8LTbHtLAZT6lurBOleBrzxXVzFnppKOeW1sLVwjptfdlYcG5nKpCMx3ZHIywEbXeM7EmN8vd-NXXDDhVbcAamsZ00M9Y8b8twVQErxcwAEA1jKE140-1VCJ-AZEEVwQ</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Nussbaum, S.</creator><creator>Smith, J.E.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>2001</creationdate><title>Modeling superscalar processors via statistical simulation</title><author>Nussbaum, S. ; Smith, J.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i245t-97bd68efcf26091db4d4d0f2bbc3d734f9ff87bedd50679198ef5ea3b1dbbff13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Analytical models</topic><topic>Computational modeling</topic><topic>Computer errors</topic><topic>Computer performance</topic><topic>Computer simulation</topic><topic>Convergence</topic><topic>Discrete event simulation</topic><topic>Predictive models</topic><topic>Space exploration</topic><topic>Statistics</topic><toplevel>online_resources</toplevel><creatorcontrib>Nussbaum, S.</creatorcontrib><creatorcontrib>Smith, J.E.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nussbaum, S.</au><au>Smith, J.E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Modeling superscalar processors via statistical simulation</atitle><jtitle>Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques</jtitle><stitle>PACT</stitle><date>2001</date><risdate>2001</risdate><spage>15</spage><epage>24</epage><pages>15-24</pages><issn>1089-796X</issn><issn>1089-795X</issn><isbn>0769513638</isbn><isbn>9780769513638</isbn><abstract>Statistical simulation is a technique for fast performance evaluation of superscalar processors. First, intrinsic statistical information is collected from a single detailed simulation of a program. This information is then used to generate a synthetic instruction trace that is fed to a simple processor model, along with cache and branch prediction statistics. Because of the probabilistic nature of the simulation, it quickly converges to a performance rate. The simplicity and simulation speed make it useful for fast design space exploration; as such, it is a good complement to conventional detailed simulation. The accuracy of this technique is evaluated for different levels of modeling complexity. Both errors and convergence properties are studied in detail. A simple instruction model yields an average error of 8% compared with detailed simulation. A more detailed instruction model reduces the error to 5% but requires about three times as long to converge.</abstract><pub>IEEE</pub><doi>10.1109/PACT.2001.953284</doi><tpages>10</tpages><oa>free_for_read</oa></addata></record>
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subjects Analytical models
Computational modeling
Computer errors
Computer performance
Computer simulation
Convergence
Discrete event simulation
Predictive models
Space exploration
Statistics
title Modeling superscalar processors via statistical simulation
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-19T18%3A57%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Modeling%20superscalar%20processors%20via%20statistical%20simulation&rft.jtitle=Proceedings%202001%20International%20Conference%20on%20Parallel%20Architectures%20and%20Compilation%20Techniques&rft.au=Nussbaum,%20S.&rft.date=2001&rft.spage=15&rft.epage=24&rft.pages=15-24&rft.issn=1089-796X&rft.isbn=0769513638&rft.isbn_list=9780769513638&rft_id=info:doi/10.1109/PACT.2001.953284&rft_dat=%3Cproquest_6IE%3E26791316%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26791316&rft_id=info:pmid/&rft_ieee_id=953284&rfr_iscdi=true