1100 V, 22.9 mΩcm2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device \vphantom {_{\int _{}}} where {L}_{\textit {ch}} = 0.8\,\,\mu \text{m} and {L}_{d} = 12\,\,\mu \text{m} shows an {R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} of 22.9 \text{m}\Omega cm 2 at a {V}_{\text {GS}} of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV 2 / {R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} of 55.5 MW/cm 2 . Devices that have different {L}_{\text {ch}} , {L}_{\text {JFET}} , {L}_{d} , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The {R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G} and {R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}} values are calculated as 17.7 and 9.0~\Omega nC, respectively, which are promising for power-integrated circuit applications.