A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device

An ultra-low power ECG processor ASIC (application specific integrated circuit) with R-wave detection and data compression is presented, which is designed for the long-term implantable cardiac monitoring (ICM) device for arrhythmia diagnosis. An adaptive derivative-based detection algorithm with low computation overhead for potential arrhythmia recording is proposed to detect arrhythmia with the occasional abnormal heart beats. In order to save as much as possible cardiac information with the limited memory size available in the ICM device, a hierarchical data buffer structure is proposed which saves 3 types of data, including the raw ECG data segments of 2 seconds, compressed ECG data segments of 45 seconds, and R-peak values and interval lengths of >2000 beat cycles. A modified swinging-door-trending (SDT) method is proposed for the ECG data compression. The ASIC has been implemented based on fully-customized near-threshold standard cells using the thick-gate transistors in 65-nm CMOS technology for low dynamic power consumption and leakage. The ASIC core occupies a die area of 1.77 mm 2 . The measured total power is 2.63 μW, which is among the ECG processors with the lowest core power consumption. It exhibits a relatively high positive precision rate ( P + ) of 99.3% with a sensitivity of 98.2%, in contrast to the similar designs in literature with the same core power consumption level. Also, an ECG data compression ratio ( CR ) of up to 17.0 has been achieved, with a good trade-off between the compression efficiency and loss.