Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model

Accurately modeling memory timing in a processor simulator is crucial for obtaining accurate and useful performance predictions. DRAM has a complex timing and reordering scheme, which results in highly varying access latencies depending on the type of operations, address stream patterns and bandwidth load. Therefore, DRAM simulators model the DRAM timings as a clocked state machine. However, some processor simulators, in particular loosely synchronized parallel simulators, assume an immediate-response memory model, requesting an immediate estimation of the memory latency. In this letter, we discuss the modeling issues in transforming a state machine DRAM simulator into an immediate-response simulator, which can be directly plugged into a processor simulator supporting an immediate-response memory model and/or a relaxed parallel simulation model. We show that the adapted model is accurate within 2 percent compared to the state machine simulator.