A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a time-to-digital-converter (TDC). The TDC will be a part of the readout Application-Specific Integrated Circuit (ASIC), called endcap timing read-out chip (ETROC), to read out low-gain avalanche detectors (LGADs) for the CMS endcap timing layer (ETL) of hig...

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