A Low-Power Time-to-Digital Converter for the CMS Endcap Timing Layer (ETL) Upgrade

We present the design and test results of a time-to-digital-converter (TDC). The TDC will be a part of the readout Application-Specific Integrated Circuit (ASIC), called endcap timing read-out chip (ETROC), to read out low-gain avalanche detectors (LGADs) for the CMS endcap timing layer (ETL) of high-luminosity large hadron collider (LHC) upgrade. One of the challenges of the ETROC design is that the TDC is required to consume less than 200 \mu \text{W} for each pixel at the nominal hit occupancy of 1%. To meet the low-power requirement, we use a single delay line for both the time of arrival (TOA) and the time over threshold (TOT) measurements without delay control. A double-strobe self-calibration scheme is used to compensate for process variation, temperature, and power supply voltage. The TDC is fabricated in a 65-nm CMOS technology. The overall performances of the TDC have been evaluated. The TOA has a bin size of 17.8 ps within its effective dynamic range of 11.6 ns. The effective measurement precision of the TOA is 5.6 and 9.9 ps with and without nonlinearity correction, respectively. The TDC block consumes 97 \mu \text{W} at the hit occupancy of 1%. Over a temperature range from 23 °C to 78 °C and a power supply voltage range from 1.05 to 1.35 V (the nominal value of 1.20 V), the self-calibrated bin size of the TOA varies within 0.4%. The measured TDC performances meet the requirements except that more tests will be performed in the future to verify that the TDC complies with the radiation tolerance specifications.