Time-shared TMR for fault-tolerant CORDIC processors

Presents a low-cost approach to concurrent error correction in high-performance CORDIC processors by using time-shared triple modular redundancy. Operands are partitioned into three sets of disjoint digits and operations are performed three times on different hardware components to correct possible...

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Hauptverfasser: Jae-Hyuck Kwak, Piuri, V., Swartzander, E.E.
Format: Tagungsbericht
Sprache:eng
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Beschreibung
Zusammenfassung:Presents a low-cost approach to concurrent error correction in high-performance CORDIC processors by using time-shared triple modular redundancy. Operands are partitioned into three sets of disjoint digits and operations are performed three times on different hardware components to correct possible errors by majority voting. The approach has limited latency increase and throughput reduction. Pipelining can be used to maintain the same throughput as a conventional design.
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.2001.941149