Power efficient semi-automatic instruction encoding for application specific instruction set processors

Power efficient semi-automatic instruction encoding for application specific instruction set processors

A novel design methodology for the implementation of control units for application specific instruction set processors (ASIPS) is described. This methodology uses automatic instruction encoding and semi-automatic generation of the hardware instruction decoder to speed up the ASIP design. Significant...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Glokler, T., Bitterlich, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Application software
Application specific processors
Casting
Design methodology
Digital signal processing
Encoding
Hardware
Instruction sets
Signal processing
Signal processing algorithms
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Beschreibung
Zusammenfassung:A novel design methodology for the implementation of control units for application specific instruction set processors (ASIPS) is described. This methodology uses automatic instruction encoding and semi-automatic generation of the hardware instruction decoder to speed up the ASIP design. Significant power savings due to optimized instruction encoding are achieved. Results for ICORE (ISS-Core), which is an ASIP for digital video broadcasting algorithms of Infineon Technologies, demonstrate the efficiency and applicability of this approach.
ISSN:1520-6149
2379-190X
DOI:10.1109/ICASSP.2001.941131