Performance Improvement of 1T DRAM by Raised Source and Drain Engineering
In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device...
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| Veröffentlicht in: | IEEE transactions on electron devices 2021-04, Vol.68 (4), p.1577-1584 |
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| container_title | IEEE transactions on electron devices |
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| creator | Ansari, Md. Hasan Raza Cho, Seongjae |
| description | In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time ( {T}_{\text {ret}} ) and larger sensing margin (SM). The designed 1T DRAM achieves {T}_{\text {ret}} \sim {330} and \sim 200 ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write "1") and energy ( 2.16\times 10^{-15} J for read "1" and 1.5\times 10^{-17} J for read "0" operations). Furthermore, it is revealed that low- \kappa spacer has an effect of increasing {T}_{\text {ret}} in the device. |
| doi_str_mv | 10.1109/TED.2021.3056952 |
| format | Article |
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Hasan Raza ; Cho, Seongjae</creator><creatorcontrib>Ansari, Md. Hasan Raza ; Cho, Seongjae</creatorcontrib><description><![CDATA[In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time (<inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} </tex-math></inline-formula>) and larger sensing margin (SM). The designed 1T DRAM achieves <inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} \sim {330} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\sim 200 </tex-math></inline-formula> ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write "1") and energy (<inline-formula> <tex-math notation="LaTeX">2.16\times 10^{-15} </tex-math></inline-formula> J for read "1" and <inline-formula> <tex-math notation="LaTeX">1.5\times 10^{-17} </tex-math></inline-formula> J for read "0" operations). Furthermore, it is revealed that low-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> spacer has an effect of increasing <inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} </tex-math></inline-formula> in the device.]]></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2021.3056952</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>CAD ; Computer aided design ; Double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) ; Dynamic random access memory ; Electric potential ; Field effect transistors ; Impact ionization ; Logic gates ; low-power operation ; Mathematical model ; Metal oxide semiconductors ; MOSFET ; MOSFETs ; one-transistor (1T) dynamic random access memory (DRAM) ; Power consumption ; Random access memory ; retention time ; Semiconductor devices ; sensing margin (SM) ; Silicon ; technology computer-aided design (TCAD) ; Transistors</subject><ispartof>IEEE transactions on electron devices, 2021-04, Vol.68 (4), p.1577-1584</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-3c247c56f01a3908fa217deda1147eece4b9e193053f99ca58779e3b455464be3</citedby><cites>FETCH-LOGICAL-c291t-3c247c56f01a3908fa217deda1147eece4b9e193053f99ca58779e3b455464be3</cites><orcidid>0000-0002-8587-4588 ; 0000-0001-8520-718X</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9354433$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9354433$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ansari, Md. Hasan Raza</creatorcontrib><creatorcontrib>Cho, Seongjae</creatorcontrib><title>Performance Improvement of 1T DRAM by Raised Source and Drain Engineering</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description><![CDATA[In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time (<inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} </tex-math></inline-formula>) and larger sensing margin (SM). The designed 1T DRAM achieves <inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} \sim {330} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\sim 200 </tex-math></inline-formula> ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write "1") and energy (<inline-formula> <tex-math notation="LaTeX">2.16\times 10^{-15} </tex-math></inline-formula> J for read "1" and <inline-formula> <tex-math notation="LaTeX">1.5\times 10^{-17} </tex-math></inline-formula> J for read "0" operations). Furthermore, it is revealed that low-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> spacer has an effect of increasing <inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} </tex-math></inline-formula> in the device.]]></description><subject>CAD</subject><subject>Computer aided design</subject><subject>Double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET)</subject><subject>Dynamic random access memory</subject><subject>Electric potential</subject><subject>Field effect transistors</subject><subject>Impact ionization</subject><subject>Logic gates</subject><subject>low-power operation</subject><subject>Mathematical model</subject><subject>Metal oxide semiconductors</subject><subject>MOSFET</subject><subject>MOSFETs</subject><subject>one-transistor (1T) dynamic random access memory (DRAM)</subject><subject>Power consumption</subject><subject>Random access memory</subject><subject>retention time</subject><subject>Semiconductor devices</subject><subject>sensing margin (SM)</subject><subject>Silicon</subject><subject>technology computer-aided design (TCAD)</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1LAzEQxYMoWKt3wUvA89ZMPjabY2mrFipKreeQzc6WLW62Zluh_70pLZ6Ggfdm3vsRcg9sBMDM02o2HXHGYSSYyo3iF2QASunM5DK_JAPGoMiMKMQ1uen7TVpzKfmAzD8w1l1sXfBI5-02dr_YYtjRrqawotPl-I2WB7p0TY8V_ez2MelcqOg0uibQWVg3ATE2YX1Lrmr33ePdeQ7J1_NsNXnNFu8v88l4kXluYJcJz6X2Kq8ZOGFYUTsOusLKAUiN6FGWBsGkFqI2xjtVaG1QlFIpmcsSxZA8nu6mrD977Hd2k1KF9NJylbqD0DlLKnZS-dj1fcTabmPTuniwwOwRmE3A7BGYPQNLloeTpUHEf7kRSkohxB92yGSr</recordid><startdate>20210401</startdate><enddate>20210401</enddate><creator>Ansari, Md. Hasan Raza</creator><creator>Cho, Seongjae</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><orcidid>https://orcid.org/0000-0002-8587-4588</orcidid><orcidid>https://orcid.org/0000-0001-8520-718X</orcidid></search><sort><creationdate>20210401</creationdate><title>Performance Improvement of 1T DRAM by Raised Source and Drain Engineering</title><author>Ansari, Md. Hasan Raza ; Cho, Seongjae</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c291t-3c247c56f01a3908fa217deda1147eece4b9e193053f99ca58779e3b455464be3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2021</creationdate><topic>CAD</topic><topic>Computer aided design</topic><topic>Double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET)</topic><topic>Dynamic random access memory</topic><topic>Electric potential</topic><topic>Field effect transistors</topic><topic>Impact ionization</topic><topic>Logic gates</topic><topic>low-power operation</topic><topic>Mathematical model</topic><topic>Metal oxide semiconductors</topic><topic>MOSFET</topic><topic>MOSFETs</topic><topic>one-transistor (1T) dynamic random access memory (DRAM)</topic><topic>Power consumption</topic><topic>Random access memory</topic><topic>retention time</topic><topic>Semiconductor devices</topic><topic>sensing margin (SM)</topic><topic>Silicon</topic><topic>technology computer-aided design (TCAD)</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ansari, Md. Hasan Raza</creatorcontrib><creatorcontrib>Cho, Seongjae</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ansari, Md. Hasan Raza</au><au>Cho, Seongjae</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Performance Improvement of 1T DRAM by Raised Source and Drain Engineering</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2021-04-01</date><risdate>2021</risdate><volume>68</volume><issue>4</issue><spage>1577</spage><epage>1584</epage><pages>1577-1584</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract><![CDATA[In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time (<inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} </tex-math></inline-formula>) and larger sensing margin (SM). The designed 1T DRAM achieves <inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} \sim {330} </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">\sim 200 </tex-math></inline-formula> ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write "1") and energy (<inline-formula> <tex-math notation="LaTeX">2.16\times 10^{-15} </tex-math></inline-formula> J for read "1" and <inline-formula> <tex-math notation="LaTeX">1.5\times 10^{-17} </tex-math></inline-formula> J for read "0" operations). Furthermore, it is revealed that low-<inline-formula> <tex-math notation="LaTeX">\kappa </tex-math></inline-formula> spacer has an effect of increasing <inline-formula> <tex-math notation="LaTeX">{T}_{\text {ret}} </tex-math></inline-formula> in the device.]]></abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TED.2021.3056952</doi><tpages>8</tpages><orcidid>https://orcid.org/0000-0002-8587-4588</orcidid><orcidid>https://orcid.org/0000-0001-8520-718X</orcidid></addata></record> |
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| subjects | CAD Computer aided design Double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) Dynamic random access memory Electric potential Field effect transistors Impact ionization Logic gates low-power operation Mathematical model Metal oxide semiconductors MOSFET MOSFETs one-transistor (1T) dynamic random access memory (DRAM) Power consumption Random access memory retention time Semiconductor devices sensing margin (SM) Silicon technology computer-aided design (TCAD) Transistors |
| title | Performance Improvement of 1T DRAM by Raised Source and Drain Engineering |
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