Performance Improvement of 1T DRAM by Raised Source and Drain Engineering

In this work, a double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) with raised source and drain (RSD) regions is utilized for application of one-transistor (1T) dynamic random access memory (DRAM) through series of validation by technology computer-aided design (TCAD) device simulation. The engineered device shows less short-channel effects (SCEs) and unwanted interband tunneling compared with the usual DG MOSFETs. As a 1T DRAM device, it demonstrates longer retention time ( {T}_{\text {ret}} ) and larger sensing margin (SM). The designed 1T DRAM achieves {T}_{\text {ret}} \sim {330} and \sim 200 ms at 27 °C and 85 °C, respectively, at 50-nm channel length. Also, the device shows higher current ratio and consumes low power (84.7 nW for write "1") and energy ( 2.16\times 10^{-15} J for read "1" and 1.5\times 10^{-17} J for read "0" operations). Furthermore, it is revealed that low- \kappa spacer has an effect of increasing {T}_{\text {ret}} in the device.