Experimental and simulation study on sub-50 nm CMOS design

CMOS devices with gate lengths down to sub-50 nm were fabricated using poly-Si gates with notches and conventional gate structures. It was shown that an optimal halo, as compared to conventional gates, is achieved when a tilted implant is performed using gates with notches. Due to optimal halo placement, up to 7% improvement in drain current for p-MOS and 15% improvement for n-MOS and simultaneously 20 nm improvement in threshold voltage roll-off were observed for notched gate devices for the same extension implant.