Fast LDPC GPU Decoder for Cloud RAN
The graphical processing unit (GPU), as a digital signal processing accelerator for cloud RAN, is investigated. This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utili...
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| Veröffentlicht in: | IEEE embedded systems letters 2021-12, Vol.13 (4), p.170-173 |
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| container_title | IEEE embedded systems letters |
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| creator | Ling, Jonathan Cautereels, Paul |
| description | The graphical processing unit (GPU), as a digital signal processing accelerator for cloud RAN, is investigated. This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have 5\times higher throughput compared to a recent GPU flooding decoder and 3\times higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. For rapid deployment and flexibility, GPUs may be suitable as cloud RAN accelerators. |
| doi_str_mv | 10.1109/LES.2021.3052714 |
| format | Article |
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This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have <inline-formula> <tex-math notation="LaTeX">5\times </tex-math></inline-formula> higher throughput compared to a recent GPU flooding decoder and <inline-formula> <tex-math notation="LaTeX">3\times </tex-math></inline-formula> higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. For rapid deployment and flexibility, GPUs may be suitable as cloud RAN accelerators.]]></description><identifier>ISSN: 1943-0663</identifier><identifier>EISSN: 1943-0671</identifier><identifier>DOI: 10.1109/LES.2021.3052714</identifier><identifier>CODEN: ESLMAP</identifier><language>eng</language><publisher>Piscataway: IEEE</publisher><subject>5G mobile communication ; 5G wireless ; Algorithms ; Clouds ; Decoding ; Digital signal processing ; Field programmable gate arrays ; Flooding ; forward error correction ; Graphics processing units ; graphics processors ; low-density parity check (LDPC) ; Message systems ; Parallel processing ; Parity check codes ; Power efficiency ; Resource utilization</subject><ispartof>IEEE embedded systems letters, 2021-12, Vol.13 (4), p.170-173</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2021</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c291t-11b8bfa239222ac9cdede89057d35cff49eb6eb88ccdc0b793bcae2ccdc3d32e3</citedby><cites>FETCH-LOGICAL-c291t-11b8bfa239222ac9cdede89057d35cff49eb6eb88ccdc0b793bcae2ccdc3d32e3</cites><orcidid>0000-0003-0108-8908 ; 0000-0001-5098-8027</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/9328563$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/9328563$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ling, Jonathan</creatorcontrib><creatorcontrib>Cautereels, Paul</creatorcontrib><title>Fast LDPC GPU Decoder for Cloud RAN</title><title>IEEE embedded systems letters</title><addtitle>LES</addtitle><description><![CDATA[The graphical processing unit (GPU), as a digital signal processing accelerator for cloud RAN, is investigated. This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have <inline-formula> <tex-math notation="LaTeX">5\times </tex-math></inline-formula> higher throughput compared to a recent GPU flooding decoder and <inline-formula> <tex-math notation="LaTeX">3\times </tex-math></inline-formula> higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. For rapid deployment and flexibility, GPUs may be suitable as cloud RAN accelerators.]]></description><subject>5G mobile communication</subject><subject>5G wireless</subject><subject>Algorithms</subject><subject>Clouds</subject><subject>Decoding</subject><subject>Digital signal processing</subject><subject>Field programmable gate arrays</subject><subject>Flooding</subject><subject>forward error correction</subject><subject>Graphics processing units</subject><subject>graphics processors</subject><subject>low-density parity check (LDPC)</subject><subject>Message systems</subject><subject>Parallel processing</subject><subject>Parity check codes</subject><subject>Power efficiency</subject><subject>Resource utilization</subject><issn>1943-0663</issn><issn>1943-0671</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2021</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kN9LwzAQx4MoOObeBV8KPrcmuSZtHkf3Q6HoUPccmuQKG9POpH3wvzd1Y_dyd_D9fu_4EHLPaMYYVU_18iPjlLMMqOAFy6_IhKkcUioLdn2ZJdySWQh7GkvkhQAxIY-rJvRJvdhUyXqzTRZoO4c-aTufVIducMn7_PWO3LTNIeDs3Kdku1p-Vs9p_bZ-qeZ1arlifcqYKU3bcFCc88Yq69BhqagoHAjbtrlCI9GUpbXOUlMoMLZBPm7ggCNM4zf_uUff_QwYer3vBv8dT2ouKZO5iMFRRU8q67sQPLb66Hdfjf_VjOqRho409EhDn2lEy8PJskPEi1wBL4UE-AOH_VhS</recordid><startdate>202112</startdate><enddate>202112</enddate><creator>Ling, Jonathan</creator><creator>Cautereels, Paul</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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This letter presents a new design for a 5G NR low-density parity check code decoder running on a GPU. The algorithm is flexibly adaptable to GPU architecture to achieve high resource utilization as well as low latency. It improves on the layered algorithm by increasing parallelism on a single code word. The flexible GPU decoder (on a 24 core GPU) was found to have <inline-formula> <tex-math notation="LaTeX">5\times </tex-math></inline-formula> higher throughput compared to a recent GPU flooding decoder and <inline-formula> <tex-math notation="LaTeX">3\times </tex-math></inline-formula> higher throughput compared to a field programmable gate array (FPGA) decoder (757K gate). The flexible GPU decoder exhibits 1/3 decoding power efficiency of the FPGA typical of general-purpose processors. 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| ispartof | IEEE embedded systems letters, 2021-12, Vol.13 (4), p.170-173 |
| issn | 1943-0663 1943-0671 |
| language | eng |
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| source | IEEE/IET Electronic Library (IEL) |
| subjects | 5G mobile communication 5G wireless Algorithms Clouds Decoding Digital signal processing Field programmable gate arrays Flooding forward error correction Graphics processing units graphics processors low-density parity check (LDPC) Message systems Parallel processing Parity check codes Power efficiency Resource utilization |
| title | Fast LDPC GPU Decoder for Cloud RAN |
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