Blanket and pocket anti punchthrough device design approaches in 0.35-/spl mu/m CMOS technology development

Short channel devices suffer from punchthrough leakage due to barrier lowering induced by drain bias (DIBL). The device engineering strategy aims at reducing leakage from surface, sub-surface and bulk current paths. In deep sub-micron devices, bulk punchthrough is the major contributor to the DIBL l...

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Bibliographische Detailangaben

Hauptverfasser:	Hussin, M.R.M., Saari, S.A.M., Rahim, A.I.A., Ayub, R.M., Ahmad, M.R.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Annealing Boron CMOS technology Electrodes Implants Isolation technology Leakage current MOS devices MOSFETs Threshold voltage
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