Blanket and pocket anti punchthrough device design approaches in 0.35-/spl mu/m CMOS technology development

Short channel devices suffer from punchthrough leakage due to barrier lowering induced by drain bias (DIBL). The device engineering strategy aims at reducing leakage from surface, sub-surface and bulk current paths. In deep sub-micron devices, bulk punchthrough is the major contributor to the DIBL leakage. This paper describes process optimization that requires some trade-offs between device parameters such as off-state current leakage, drive current and threshold voltage, to meet technology specifications. In this work we optimize well, channel, pocket and drain implant and anneal parameters to achieve the desired device characteristics.