Single and dual damascene integration of a spin-on porous ultra low-k material

Single and dual damascene integration of a spin-on porous ultra low-k material

For future high performance logic semiconductor products it is essential to lower the dielectric constant k of the intra- and interlayer isolators in combination with Cu single and dual damascene metallisation. In this paper we report on the first successful single and dual damascene integration of...

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Hauptverfasser: Mosig, K., Jacobs, T., Kofron, P., Daniels, M., Brennan, K., Gonzales, A., Augur, R., Wetzel, J., Havemann, R., Shiota, A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Damascene integration
Dielectric constant
Dielectric materials
Etching
Isolators
Logic
Metallization
Resists
Semiconductor materials
Strips
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Zusammenfassung:For future high performance logic semiconductor products it is essential to lower the dielectric constant k of the intra- and interlayer isolators in combination with Cu single and dual damascene metallisation. In this paper we report on the first successful single and dual damascene integration of a porous methylsilsesquioxane based spin-on dielectric, JSR LKD. Deposition, etch, resist strip, clean and CMP behaviour and electrical results from both single and dual damascene integration are discussed.
DOI:10.1109/IITC.2001.930087