High-Performance GaN Vertical p-i-n Diodes via Silicon Nitride Shadowed Selective-Area Growth and Optimized FGR- and JTE-Based Edge Termination

In this work, we develop highly efficient ET schemes based on a selective-area processing methodology that can effectively stymie device leakage, resulting in reliable device operation. In particular, we demonstrate plasma-assisted molecular-beam epitaxy (PAMBE) facilitated silicon nitride shadowed selective-area growth (SNS-SAG) technique, capable of producing smooth GaN interfaces and sidewalls as an enabling technology for high-performance vertical GaN power devices. SNS-SAG is shown to reduce leakage current by at least four orders of magnitude compared to a dry etched device. Floating guard ring (FGR) and junction termination extension (JTE) based ET designs for GaN p-i-n diodes for punchthrough operation have been simulated and analyzed in order to develop SNS-SAG compatible space-modulated junction termination extension (SM-JTE) schemes capable of achieving maximum reverse blocking efficiency >98% while maintaining a wide doping window of up to \sim \,\,5\times 10^{17} cm −3 at a minimum reverse blocking efficiency of ~ 90% extending well into high 10 17 cm −3 range ( \sim \,\,8\times 10^{17} cm −3 ). In conjunction with the proposed SNS-SAG technique, SM-JTE schemes have the prospects to offer reliable GaN vertical power device operation.