Microstructure and electrical properties of Ge- and Si-nanoclusters in implanted gate oxide for embedded memory applications

MOSFETs with gate oxides containing nanoclusters (Si,Ge) fabricated with different techniques (implantation, LPCVD, sputtering) are a very promising approach for future memories. This contribution reports on results obtained on Si- or Ge-implanted MOS capacitors and transistors. By varying the implantation and annealing parameters the Si or Ge depth profile and the cluster size and distribution can be controlled. The experimental results are explained by a theoretical model, which is based on TRIM calculations, rate-equation studies and 3D kinetic Monte Carlo simulations. The electrical properties of gate-SiO/sub 2/ containing Si- or Ge-nanoclusters are investigated in detail with emphasis on its feasibility for embedded memories for system on chip applications.