A network processor architecture for flexible QoS control in very high-speed line interfaces

A network processor architecture for flexible QoS control in very high-speed line interfaces

We developed a network processor architecture that can be used for very high-speed line interfaces of carrier-class backbone routers and switches. Because advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Shimonishi, H., Murase, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Communication system control
Costs
Delay
Intelligent networks
Parallel processing
Pipeline processing
Quality of service
Scheduling algorithm
Spine
Switches
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Beschreibung
Zusammenfassung:We developed a network processor architecture that can be used for very high-speed line interfaces of carrier-class backbone routers and switches. Because advanced queuing and packet scheduling mechanisms are implemented as a software routine without the need for any special hardware components, the architecture provides a flexible QoS control mechanism and enables effective header handling.
DOI:10.1109/HPSR.2001.923669