Scan wheel-a technique for interfacing a high speed scan-path with a slow speed tester
A novel interface architecture allows slow-speed test equipment to control and access scan registers operating at the full clock rate of the chip or the system. The architecture requires simple on-chip hardware and works with a minimal number of chip pins.
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Format: | Tagungsbericht |
Sprache: | eng |
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Zusammenfassung: | A novel interface architecture allows slow-speed test equipment to control and access scan registers operating at the full clock rate of the chip or the system. The architecture requires simple on-chip hardware and works with a minimal number of chip pins. |
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DOI: | 10.1109/VTS.2001.923424 |