The effects of plasma-induced damage on transistor degradation and the relationship to field programmable gate array performance

The impact of plasma-induced damage on the speed performance of a field programmable gate array (FPGA) is presented. It was found that FPGA speed degradation induced by product reliability burn-in was directly related to a large negative threshold voltage (V/sub t/) shift of the surface channel PMOS induced by negative bias temperature (BT) stress. Such negative bias temperature instability (NBTI) in the PMOS was shown to be related to specific back-end plasma processing steps. An overall reduction in NBTI of the PMOSFET was observed when certain plasma processing steps were eliminated which in turn resulted in the reduction of FPGA performance degradation.