A parallel genetic approach to the gate sizing problem of VLSI integrated circuits

This paper describes the implementation of a software CAD (computer aided design) tool, applied to the sizing problem of standard cells in VLSI integrated circuits. Unfortunately, the sizing problem belongs to the class of NP-complete problems, and the size of VLSI circuits may be huge. As a consequence, we studied heuristic solutions in order to solve this problem. This software performs circuit timing optimization, based on an evolutionary approach. The genetic algorithm is a meta-heuristic which gives near-optimal solutions with polynomial running times.