Physical design of a fourth-generation POWER GHz microprocessor

Physical design of a fourth-generation POWER GHz microprocessor

The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnec...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) 2001, p.232-233
Hauptverfasser: Anderson, C.J., Petrovick, J., Keaty, J.M., Warnock, J., Nussbaum, G., Tendier, J.M., Carter, C., Chu, S., Clabes, J., DiLullo, J., Dudley, P., Harvey, P., Krauter, B., LeBlanc, J., Pong-Fei Lu, McCredie, B., Plum, G., Restle, P.J., Runyon, S., Scheuermann, M., Schmidt, S., Wagoner, J., Weiss, R., Weitzel, S., Zoric, B.
Format: Artikel
Sprache:eng
Schlagworte:
Capacitance
Circuit testing
Circuit topology
Clocks
CMOS technology
Contracts
Laboratories
Microprocessors
Timing
Wiring
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The fourth-generation POWER processor chip contains 170M transistors and includes 2 microprocessor cores, shared L2, directory for an off-chip L3, and all logic needed to interconnect multiple chips to form an SMP. It is implemented in a 0.18 /spl mu/m SOI technology, with 7 layers of Cu interconnect, and functions in systems at 1.1 GHz, and dissipates 115 W at 1.5 V.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2001.912617