FinFET-a quasi-planar double-gate MOSFET
The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations s...
Gespeichert in:
Hauptverfasser: | , , , , , , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 119 |
---|---|
container_issue | |
container_start_page | 118 |
container_title | |
container_volume | |
creator | Tang, S.H. Chang, L. Lindert, N. Yang-Kyu Choi Wen-Chin Lee Xuejue Huang Subramanian, V. Bokor, J. Tsu-Jae King Chenming Hu |
description | The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations show FinFET circuit performance exceeds that of advanced single gate MOSFETs. |
doi_str_mv | 10.1109/ISSCC.2001.912568 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_ieee_primary_912568</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>912568</ieee_id><sourcerecordid>26736362</sourcerecordid><originalsourceid>FETCH-LOGICAL-i118t-9fc110f93caa89b9304deb42b329ce8930d3b7706a18d7e4ecf6fc6da35ea3a43</originalsourceid><addsrcrecordid>eNotkE9Lw0AUxBf_gG31A-ipJ_Gy9e2-5GX3KMFqodJD9RxekheJpE2abQ5-ewPxNMzwYxhGqXsDK2PAP2_2-zRdWQCz8sbG5C7UzGJC2hHQpZpD4gCJwMVXagbGo6YY4UbNQ_gBgNiTm6mndX1cv35qXp4GDrXuGj5yvyzbIW9Ef_NZlh-7_UjcquuKmyB3_7pQX2Oavuvt7m2Tvmx1bYw7a18V47jKY8HsfO4RolLyyOZofSFu9CXmSQLExpWJRFJUVBVUMsbCyBEu1OPU2_XtaZBwzg51KKQZd0k7hMxSgoRkR_BhAmsRybq-PnD_m01P4B8xVk5d</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>26736362</pqid></control><display><type>conference_proceeding</type><title>FinFET-a quasi-planar double-gate MOSFET</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Tang, S.H. ; Chang, L. ; Lindert, N. ; Yang-Kyu Choi ; Wen-Chin Lee ; Xuejue Huang ; Subramanian, V. ; Bokor, J. ; Tsu-Jae King ; Chenming Hu</creator><creatorcontrib>Tang, S.H. ; Chang, L. ; Lindert, N. ; Yang-Kyu Choi ; Wen-Chin Lee ; Xuejue Huang ; Subramanian, V. ; Bokor, J. ; Tsu-Jae King ; Chenming Hu</creatorcontrib><description>The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations show FinFET circuit performance exceeds that of advanced single gate MOSFETs.</description><identifier>ISSN: 0193-6530</identifier><identifier>ISBN: 0780366085</identifier><identifier>ISBN: 9780780366084</identifier><identifier>EISSN: 2376-8606</identifier><identifier>DOI: 10.1109/ISSCC.2001.912568</identifier><language>eng</language><publisher>IEEE</publisher><subject>Capacitance ; Circuit simulation ; CMOS technology ; Dielectrics ; Electrodes ; FinFETs ; Leakage current ; Manufacturing processes ; Medical simulation ; MOSFET circuits</subject><ispartof>2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.118-119</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/912568$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,4048,4049,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/912568$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tang, S.H.</creatorcontrib><creatorcontrib>Chang, L.</creatorcontrib><creatorcontrib>Lindert, N.</creatorcontrib><creatorcontrib>Yang-Kyu Choi</creatorcontrib><creatorcontrib>Wen-Chin Lee</creatorcontrib><creatorcontrib>Xuejue Huang</creatorcontrib><creatorcontrib>Subramanian, V.</creatorcontrib><creatorcontrib>Bokor, J.</creatorcontrib><creatorcontrib>Tsu-Jae King</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><title>FinFET-a quasi-planar double-gate MOSFET</title><title>2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)</title><addtitle>ISSCC</addtitle><description>The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations show FinFET circuit performance exceeds that of advanced single gate MOSFETs.</description><subject>Capacitance</subject><subject>Circuit simulation</subject><subject>CMOS technology</subject><subject>Dielectrics</subject><subject>Electrodes</subject><subject>FinFETs</subject><subject>Leakage current</subject><subject>Manufacturing processes</subject><subject>Medical simulation</subject><subject>MOSFET circuits</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>0780366085</isbn><isbn>9780780366084</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2001</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkE9Lw0AUxBf_gG31A-ipJ_Gy9e2-5GX3KMFqodJD9RxekheJpE2abQ5-ewPxNMzwYxhGqXsDK2PAP2_2-zRdWQCz8sbG5C7UzGJC2hHQpZpD4gCJwMVXagbGo6YY4UbNQ_gBgNiTm6mndX1cv35qXp4GDrXuGj5yvyzbIW9Ef_NZlh-7_UjcquuKmyB3_7pQX2Oavuvt7m2Tvmx1bYw7a18V47jKY8HsfO4RolLyyOZofSFu9CXmSQLExpWJRFJUVBVUMsbCyBEu1OPU2_XtaZBwzg51KKQZd0k7hMxSgoRkR_BhAmsRybq-PnD_m01P4B8xVk5d</recordid><startdate>2001</startdate><enddate>2001</enddate><creator>Tang, S.H.</creator><creator>Chang, L.</creator><creator>Lindert, N.</creator><creator>Yang-Kyu Choi</creator><creator>Wen-Chin Lee</creator><creator>Xuejue Huang</creator><creator>Subramanian, V.</creator><creator>Bokor, J.</creator><creator>Tsu-Jae King</creator><creator>Chenming Hu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>2001</creationdate><title>FinFET-a quasi-planar double-gate MOSFET</title><author>Tang, S.H. ; Chang, L. ; Lindert, N. ; Yang-Kyu Choi ; Wen-Chin Lee ; Xuejue Huang ; Subramanian, V. ; Bokor, J. ; Tsu-Jae King ; Chenming Hu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i118t-9fc110f93caa89b9304deb42b329ce8930d3b7706a18d7e4ecf6fc6da35ea3a43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2001</creationdate><topic>Capacitance</topic><topic>Circuit simulation</topic><topic>CMOS technology</topic><topic>Dielectrics</topic><topic>Electrodes</topic><topic>FinFETs</topic><topic>Leakage current</topic><topic>Manufacturing processes</topic><topic>Medical simulation</topic><topic>MOSFET circuits</topic><toplevel>online_resources</toplevel><creatorcontrib>Tang, S.H.</creatorcontrib><creatorcontrib>Chang, L.</creatorcontrib><creatorcontrib>Lindert, N.</creatorcontrib><creatorcontrib>Yang-Kyu Choi</creatorcontrib><creatorcontrib>Wen-Chin Lee</creatorcontrib><creatorcontrib>Xuejue Huang</creatorcontrib><creatorcontrib>Subramanian, V.</creatorcontrib><creatorcontrib>Bokor, J.</creatorcontrib><creatorcontrib>Tsu-Jae King</creatorcontrib><creatorcontrib>Chenming Hu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tang, S.H.</au><au>Chang, L.</au><au>Lindert, N.</au><au>Yang-Kyu Choi</au><au>Wen-Chin Lee</au><au>Xuejue Huang</au><au>Subramanian, V.</au><au>Bokor, J.</au><au>Tsu-Jae King</au><au>Chenming Hu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>FinFET-a quasi-planar double-gate MOSFET</atitle><btitle>2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177)</btitle><stitle>ISSCC</stitle><date>2001</date><risdate>2001</risdate><spage>118</spage><epage>119</epage><pages>118-119</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>0780366085</isbn><isbn>9780780366084</isbn><abstract>The quasi-planar FinFET structure has device characteristics similar to those of the conventional MOSFET. Inserting FinFET into CMOS technology requires no change in circuit architecture or layout/design tools, providing a smooth transition to post-planar CMOS technology. 2D mixed-mode simulations show FinFET circuit performance exceeds that of advanced single gate MOSFETs.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2001.912568</doi><tpages>2</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0193-6530 |
ispartof | 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.118-119 |
issn | 0193-6530 2376-8606 |
language | eng |
recordid | cdi_ieee_primary_912568 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Capacitance Circuit simulation CMOS technology Dielectrics Electrodes FinFETs Leakage current Manufacturing processes Medical simulation MOSFET circuits |
title | FinFET-a quasi-planar double-gate MOSFET |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T12%3A42%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=FinFET-a%20quasi-planar%20double-gate%20MOSFET&rft.btitle=2001%20IEEE%20International%20Solid-State%20Circuits%20Conference.%20Digest%20of%20Technical%20Papers.%20ISSCC%20(Cat.%20No.01CH37177)&rft.au=Tang,%20S.H.&rft.date=2001&rft.spage=118&rft.epage=119&rft.pages=118-119&rft.issn=0193-6530&rft.eissn=2376-8606&rft.isbn=0780366085&rft.isbn_list=9780780366084&rft_id=info:doi/10.1109/ISSCC.2001.912568&rft_dat=%3Cproquest_6IE%3E26736362%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26736362&rft_id=info:pmid/&rft_ieee_id=912568&rfr_iscdi=true |