Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

DLL and improved I/O circuits are for 500 Mb/s/pin DDR SDRAM. This digitally-controlled DLL has inherent duty cycle correction capability, enabling fast re-locking upon standby-mode exit. Data input circuits, such as internal delay control and digital sense amplifier, reduce setup/hold window to 0.3...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Jung-Bae Lee, Kyu-Hyoun Kim, Changsik Yoo, Sangbo Lee, One-Gyun Na, Chan-Yong Lee, Ho-Young Song, Jong-Soo Lee, Zi-Hyoun Lee, Ki-Woong Yeom, Hoi-Joo Chung, Il-Won Seo, Moo-Sung Chae, Yun-Ho Choi, Soo-In Cho
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Added delay
Circuits
Clocks
Delay effects
DRAM chips
Latches
Phase detection
Random access memory
Uncertainty
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:DLL and improved I/O circuits are for 500 Mb/s/pin DDR SDRAM. This digitally-controlled DLL has inherent duty cycle correction capability, enabling fast re-locking upon standby-mode exit. Data input circuits, such as internal delay control and digital sense amplifier, reduce setup/hold window to 0.3 ns. The output data driver has 62% decreased pattern-dependent skew.
ISSN:0193-6530
2376-8606
DOI:10.1109/ISSCC.2001.912550