Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits

The continuously growing complexity of digital circuits and shortening time-to-market has put pressure on the verification methodology. To reach this goal, automatic correction of design bugs has become necessary. Existing methods for automatic correction, suffer from consuming so much time and memo...

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Veröffentlicht in:	IEEE transactions on circuits and systems. II, Express briefs Express briefs, 2020-12, Vol.67 (12), p.3063-3067
Hauptverfasser:	Alizadeh, Bijan, Abadi, Yasaman
Format:	Artikel
Sprache:	eng
Schlagworte:	auto-correction Clocks Computer bugs Debugging Digital electronics Fault detection Logic gates Multiplexing optimization reusing test pattern generation
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