Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits

The continuously growing complexity of digital circuits and shortening time-to-market has put pressure on the verification methodology. To reach this goal, automatic correction of design bugs has become necessary. Existing methods for automatic correction, suffer from consuming so much time and memory usage which makes them mostly inapplicable for large circuits. Our main idea to come up with a solution is reusing partially corrected circuits in the process of finding the final solution. Experimental results show that, in comparison with existing methods, our method can accurately detect bugs and correct them up to 2.3× faster with less than half of memory usage in comparison with existing methods due to decreasing the number of generated solutions by 2.1× and reducing the size of the SAT problem by 3×.