A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

A 2-V 900-MHz monolithic CMOS dual-loop frequency synthesizer for GSM receivers

A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-/spl mu/m CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm/sup 2/ and consumes a low power of 34 mW. The measured p...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 2001-02, Vol.36 (2), p.204-216
Hauptverfasser: Yan, W.S.T., Luong, H.C.
Format: Artikel
Sprache:eng
Schlagworte:
Circuits
CMOS
CMOS technology
Consumption
Electric potential
Energy consumption
Frequency synthesizers
GSM
Low-noise amplifiers
Noise measurement
Offsets
Phase measurement
Phase noise
Receivers
Semiconductor device measurement
Voltage
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 900-MHz monolithic CMOS dual-loop frequency synthesizer suitable for GSM receivers is presented. Implemented in a 0.50-/spl mu/m CMOS technology and at a 2-V supply voltage, the dual-loop frequency synthesizer occupies a chip area of 2.64 mm/sup 2/ and consumes a low power of 34 mW. The measured phase noise of the synthesizer is -121.8 dBc/Hz at 600-kHz offset, and the measured spurious levels are -79.5 and -82.0 dBc at 1.6 and 11.3 MHz offset, respectively.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.902761