Defect localization using physical design and electrical test information

Defect localization using physical design and electrical test information

In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to corr...

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Bibliographische Detailangaben
Hauptverfasser: Stanojevic, Z., Balachandran, H., Walker, D.M.H., Lakhani, F., Jandhyala, S.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Automatic test pattern generation
Circuit faults
Circuit testing
Failure analysis
Fault diagnosis
Inspection
Instruments
Logic testing
Scanning electron microscopy
System testing
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Beschreibung
Zusammenfassung:In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injected via FIB. Preliminary failure analysis results on production defects are promising.
ISSN:1078-8743
2376-6697
DOI:10.1109/ASMC.2000.902568