Drain-Erase Scheme in Ferroelectric Field-Effect Transistor-Part I: Device Characterization
Ferroelectric-doped HfO 2 -based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of FeFET-based 3-D NAND architecture for both in situ t...
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Veröffentlicht in: | IEEE transactions on electron devices 2020-03, Vol.67 (3), p.955-961 |
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Sprache: | eng |
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Zusammenfassung: | Ferroelectric-doped HfO 2 -based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in NAND-like structure, we propose and experimentally demonstrate the drain-erase scheme to enable the individual cell's program/erase/inhibition, which is necessary for individual weight update in in situ training. We describe the device characterization of different drain-erase conditions and results in this article. The experimental conditions are characterized on 22-nm fully depleted silicon-on-insulator (FDSOI) and 28-nm high- {k} metal gate (HKMG) FeFET devices from GLOBALFOUNDRIES. With appropriate biasing, up to 10 4 ON/OFF ratio could be achieved by drain-erase. The 3-D NAND array architecture design and verification for in-memory computing will be described in Part II of this article. |
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ISSN: | 0018-9383 1557-9646 |
DOI: | 10.1109/TED.2020.2969401 |