Design-for-testability of the FLOVA

Design-for-testability of the FLOVA

This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Daehan Youn, Ohyoung Song, Hoon Chang
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Acceleration
Clocks
CMOS technology
Design for testability
Flip-flops
Packaging
Registers
Testing
Very large scale integration
VLIW
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Beschreibung
Zusammenfassung:This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point processing units/the embedded memory units, and the I/O cells, respectively.
DOI:10.1109/APASIC.2000.896972