An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting g_{m}/I_{D} and reducing noise. Moreover, it greatly reduces...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2020-04, Vol.55 (4), p.1011-1022 |
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| container_title | IEEE journal of solid-state circuits |
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| creator | Tang, Xiyuan Shen, Linxiao Kasap, Begum Yang, Xiangxing Shi, Wei Mukherjee, Abhishek Pan, David Z. Sun, Nan |
| description | This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting g_{m}/I_{D} and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46- \mu \text{V} input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge. |
| doi_str_mv | 10.1109/JSSC.2019.2960485 |
| format | Article |
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The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting <inline-formula> <tex-math notation="LaTeX">g_{m}/I_{D} </tex-math></inline-formula> and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46-<inline-formula> <tex-math notation="LaTeX">\mu \text{V} </tex-math></inline-formula> input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.]]></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2019.2960485</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Amplifier design ; Amplifiers ; Common-mode rejection ; dynamic biasing ; dynamic comparator ; Energy efficiency ; energy efficient ; Inverters ; latch-type comparator ; low-noise ; Noise reduction ; Power efficiency ; strong-arm (SA)</subject><ispartof>IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.1011-1022</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2020</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c336t-6bd0410b54b6dcec620decf5c387e45342570acad5eee819e14aa0ec1e4a05e03</citedby><cites>FETCH-LOGICAL-c336t-6bd0410b54b6dcec620decf5c387e45342570acad5eee819e14aa0ec1e4a05e03</cites><orcidid>0000-0001-7933-3673 ; 0000-0001-8712-2884 ; 0000-0002-5543-7870 ; 0000-0001-5894-2883 ; 0000-0002-5705-2501 ; 0000-0002-5536-8385 ; 0000-0003-2181-9042</orcidid></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/8947992$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/8947992$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Tang, Xiyuan</creatorcontrib><creatorcontrib>Shen, Linxiao</creatorcontrib><creatorcontrib>Kasap, Begum</creatorcontrib><creatorcontrib>Yang, Xiangxing</creatorcontrib><creatorcontrib>Shi, Wei</creatorcontrib><creatorcontrib>Mukherjee, Abhishek</creatorcontrib><creatorcontrib>Pan, David Z.</creatorcontrib><creatorcontrib>Sun, Nan</creatorcontrib><title>An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description><![CDATA[This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting <inline-formula> <tex-math notation="LaTeX">g_{m}/I_{D} </tex-math></inline-formula> and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46-<inline-formula> <tex-math notation="LaTeX">\mu \text{V} </tex-math></inline-formula> input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.]]></description><subject>Amplifier design</subject><subject>Amplifiers</subject><subject>Common-mode rejection</subject><subject>dynamic biasing</subject><subject>dynamic comparator</subject><subject>Energy efficiency</subject><subject>energy efficient</subject><subject>Inverters</subject><subject>latch-type comparator</subject><subject>low-noise</subject><subject>Noise reduction</subject><subject>Power efficiency</subject><subject>strong-arm (SA)</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2020</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kEtLw0AUhQdRsFZ_gLgJuE6880pmliW2tVJwUUV3w3RyU6c0Dyep0H9vSoury4XvnAMfIfcUEkpBP72uVnnCgOqE6RSEkhdkRKVUMc341yUZAVAVawZwTW66bju8Qig6IvNJHU1rDJtDPC1L7zzWfZQ3VWuD7ZsQffr-O3o-1LbyLprtGtv7ehMt6l8MPYZoUrU7X3oMt-SqtLsO7853TD5m0_f8JV6-zRf5ZBk7ztM-TtcFCAprKdZp4dClDAp0pXRcZSgkF0xmYJ0tJCIqqpEKawEdRWFBIvAxeTz1tqH52WPXm22zD_UwaRhXnDOtpR4oeqJcaLouYGna4CsbDoaCOfoyR1_m6MucfQ2Zh1PGD9P_vNIi05rxPx2XZuM</recordid><startdate>20200401</startdate><enddate>20200401</enddate><creator>Tang, Xiyuan</creator><creator>Shen, Linxiao</creator><creator>Kasap, Begum</creator><creator>Yang, Xiangxing</creator><creator>Shi, Wei</creator><creator>Mukherjee, Abhishek</creator><creator>Pan, David Z.</creator><creator>Sun, Nan</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting <inline-formula> <tex-math notation="LaTeX">g_{m}/I_{D} </tex-math></inline-formula> and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46-<inline-formula> <tex-math notation="LaTeX">\mu \text{V} </tex-math></inline-formula> input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. 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| subjects | Amplifier design Amplifiers Common-mode rejection dynamic biasing dynamic comparator Energy efficiency energy efficient Inverters latch-type comparator low-noise Noise reduction Power efficiency strong-arm (SA) |
| title | An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier |
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